The computer industry has experienced a rapid evolution in technology, particularly in semiconductor memory capabilities. The increase in the densities of semiconductor memory chips, particularly random access memory (hereinafter "RAM") chips, has dramatically increased the amount of memory available in a computer system while reducing the number of memory chips required for a particular application. A drawback to this technological advance is that the increase in RAM chip densities has also resulted in a higher error rate.
Error correcting codes ("ECCs") have been used in semiconductor memory systems to increase reliability while maintaining data integrity. In prior ECC applications, memory array chips are usually organized so that errors generated in a chip failure can be corrected by the ECC. The standard memory array design utilizes a one-bit-per-chip organization. In this organization, each bit of a data word is stored in a different chip, thus, a 32 bit data word would require 32 memory chips. Any type of chip failure would corrupt only one bit of the data word.
Error correction for semiconductor memories has traditionally been accomplished with Hamming codes. Such codes are effective for isolated soft errors, i.e., random reversal of bits or hard errors, i.e., a permanently inoperative bit. These codes have the capability of single bit error correction and are easily extended to provide double bit error detection. Hamming codes are effective with memory arrays of a one-bit-per-chip configuration since most single RAM chip failures can only affect a single bit of the data word. However, with many recent architectures, it has become desirable to use four bit wide RAM chips. With four bit wide RAMs, several RAM failure mechanisms can result in two, three, or four bits in error. Accordingly, the traditional Hamming codes are less effective if four bit wide RAMs are used. The difficulty with an ECC in such a system is that if one chip fails, four data bits will be unreliable. The ECC of such a system must be able to correct four bits per chip in the 32 bit data word. The solution to this problem is to use an error correcting code optimized for correcting units of four bit quantities instead of one bit quantities. The class of error correcting codes known as Bose-Chaudhuri-Hocquenghem ("BCH") codes provides such an optimization. BCH codes are known to be capable of detecting and correcting multiple bit errors. Reed-Solomon codes, a subset of BCH codes, are also known to be capable of detecting and correcting multiple bit errors. The basic theoretical considerations pertinent to the use of Reed-Solomon codes for detecting and correcting data errors are set forth in W. W. Peterson and E. J. Weldon's book, Error Correcting Codes, published by the MIT Press, Cambridge, Massachusetts. Reed-Solomon codes are widely used for disk error correction because of their multiple burst error correction capability. However, for disk applications the correction algorithms are based on sequential state machines, or even software routines. The use of sequential logic or software routines in a semiconductor RAM application would be prohibitively slow.
To further increase the reliability and data integrity of a memory system, other means for detecting errors have also been employed. For example, a data word read from an incorrect memory location may be undetected by the ECC logic. Prior memory systems have included a separate address parity check which insures that data is read from the appropriate memory location. Without such a check, data read from an erroneous address could appear correct. A further error condition which may be undetected is the catastrophic condition of a data word containing all ones or all zeros.
While the prior art provides an adequate method of detecting and correcting errors in digital data, there is a need for advancement. In particular, in semiconductor memory systems comprising multiple-bits-per-chip memories, fast processing speed, reliability and data integrity are essential. Thus, it is imperative to provide an error correcting scheme which minimizes processing speed while increasing reliability and data integrity.